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MD1711
High Speed, Integrated Ultrasound Driver IC
Features
Drives two ultrasound transducer channels Generates 5-level waveform Drives 12 high voltage MOSFETs 2.0A source and sink peak current Up to 20MHz output frequency 12V/ns slew rate 3ns matched delay times Second harmonic is less than -40dB Two separate gate drive voltages 1.8V to 3.3V CMOS logic interface
General Description
The Supertex MD1711 is an IC for a two-channel, 5level, high voltage and high-speed transmitter driver. It is designed for medical ultrasound imaging applications but can also be used for metal flaw detection, nondestructive evaluation, and driving piezoelectric transducers. The MD1711 is a two-channel logic controller circuit with low impedance MOSFET gate drivers. There are two sets of control logic inputs, one for channel A and one for Channel B. Each channel consists of three pairs of MOSFET gate drivers. These drivers are designed to match the drive requirements of the Supertex TC6320. The MD1711 drives six TC6320s. Each pair an N-channel and a P-channel MOSFET. They are designed to have the same impedance and can provide peak currents of over 2.0 amps.
Applications
Medical ultrasound imaging Piezoelectric transducer drivers Metal flaw detection Nondestructive evaluation Sonar Transmitter
Typical Application Circuit (1 of 2 Channels)
+5 V
0.22 F
+1 0 V
-1 0 V
0.22 F
+1 0 V
0.22 F
0.22F 0.22 F
+10V FB 6
0.1F
TC6320
+100V VPP1
1F
40 36 35 DVDD2 AVDD1
33 45
43 DGND
42
31
DGND DVSS DVDD1
DVDD1 30 DGND
DV DD2
OUTPA1
EN SEL POSA / POS1A NEGA / NEG1A HVEN1A / POS2A HVEN2A / NEG2A ClampA
+3 . 3 V 0.1 F
47 13 1 2
39
Control Logic & Level Translator
10nF
DV DD2
OUTNA1
37
10nF
VNN 1 -100V
1F
3 4
DV DD1
+50V
VPP2
1F
5 46
OUTPA2
MD1711
VL L
41
DV DD1
10nF
(1/2 of I/O)
OUTNA2
34 48
0.1 F
10nF
VNN2 -50V 0V
1F
AV S S
Transducer
0.1 F
14 15
AV S S SU B OUTPA3
AV SS VSS
DV DD 1
44
OU TNA3
32 -10V AGND DGND DVDD1 DVSS DVDD 2 DVDD1 DGND DVDD 2 0V
7
0
18
19
16
21
28
26 25
0.22F +10V -10V +10V +5V 0
1
Rev.12
011005
MD1711
Ordering Information
Package Option
48-Lead LQFP/TQFP (1.4mm)
MD1711FG MD1711FG-G
* 10z. 4-layer 3x4inch PCB -G indicates package is RoHS "Green" compliant
Thermal Resistance JA
50C/W*
Absolute Maximum Ratings*
VLL, Logic Supply AVDD1, DVDD1, Positive Gate Drive Supply DVDD2, Positive Gate Drive Supply AVSS, DVSS Negative Gate Drive Supply Storage temperature Junction temperature Power Dissipation -0.5V to +5.5V -0.5V to +15V -0.5V to +15V -15V to +0.5V -65C to 150C 125C 1.2W
*Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is not implied. Continuous operation of the device at the absolute rating level may affect device reliability. All voltages are referenced to device ground.
Operating Supply Voltages and Currents
(Over operating conditions unless otherwise specified, AVDD1 = DVDD1 = DVDD2 = 10V, AVSS = DVSS = -10V, VLL = 3.3V, TA = 25C)
Sym
VLL AVDD1 DVDD1 DVDD2 AVSS, DVSS IVLL IAVDD1 IAVSS & IDVSS IDVDD1 IDVDD2 IAVDD1Q IAVSSQ IDVDD1Q IDVDD2Q IVLLQ
Parameter
Logic Supply Positive Drive Bias Supply Positive Gate Drive Supply Positive Gate Drive Supply Negative Gate Drive and Bias Supply Logic Supply Current Positive Bias Current Negative Drive and Bias Supply Current Positive Drive Current 1 Positive Drive Current 2 VAVDD1 quiescent current VAVSS quiescent current VDVDD1 quiescent current VDVDD2 quiescent current Logic Supply Current
Min
+1.8 +8.0 +4.75 +4.75 -12.0
Typ
+3.3 +10
Max
+5.5 +12.6 +12.6 +12.6
Units
V V V V V mA mA
Note
-10 2.0 5.0 20 55 13 2.0 0.75
-8.0
All channel on at 5.0Mhz, No load mA mA mA mA mA 10 10 1.0 A A mA EN = low, All inputs low or high. DVDD2 = 5.0V, All channel on at 5.0Mhz, No load
2
MD1711
DC Electrical Characteristics
(Over operating conditions unless otherwise specified, AVDD1 = DVDD1 = DVDD2 = 10V, AVSS = DVSS = -10V, VLL = 3.3V, TA = 0 to 70C)
P-Channel Gate Driver Outputs
Sym RSINK
RSOURCE ISINK ISOURCE
Parameter Output sink resistance
Output source resistance Peak output sink current Peak output source current
Min
Typ
Max 6.0
6.0
Units
A A
Conditions ISINK = 100mA
ISOURCE = 100mA
2.0 2.0
N-Channel Gate Driver Outputs
Sym RSINK
RSOURCE ISINK ISOURCE
Parameter Output sink resistance
Output source resistance Peak output sink current Peak output source current
Min
Typ
Max 10
10
Units
A A
Conditions ISINK = 100mA
ISOURCE = 100mA
1.5 1.5
Logic Inputs
Sym VIH
VIL IIH IIL
Parameter Input logic high voltage
Input logic low voltage Input logic high current Input logic low current
Min 0.8VLL
0 -1.0
Typ
Max VLL
0.2VLL 1.0
Units V
V A A
Conditions
AC Electrical Characteristics
(Over operating conditions unless otherwise specified, AVDD1 = DVDD1 = DVDD2 = 10V, AVSS = DVSS = -10V, VLL = 3.3V, TA = 0 to 70C)
Sym
fOUT tPH tPL tr tf tdm tDLAY SR HD2
Parameter
Output frequency range Propagation delay when output is from low to high Propagation delay when output is from high to low Output rise time Output fall time Delay time matching Output jitter Output slew rate 2 harmonic distortion
nd
Min
Typ
Max
20
Units
MHz ns ns ns ns
Conditions
19 19 8.0 8.0 3.0 30 12 -40
No load, See timing diagram No load, See timing diagram 1000pF load, see timing diagram 1000pF load, see timing diagram No load, From device to device Standard deviation of td samples (1k) Measured at TC6320 output with 100 Load
ns ps V/ns dB
Power-Up Sequence
1 2 AVSS , DVSS VLL, AVDD1, DVDD1 & DVDD2 Negative Gate Drive Supply and Substrate Bias Logic Supply, Positive Gate Drive Supply and Bias
3
MD1711
Truth Table for Channels A and B (For SEL = L)
Logic Control Inputs SEL EN HVEN1/ POS2 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 0 X HVEN2/ NEG2 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 X Clamp 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 X POS/ POS1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 X NEG/ NEG1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 X VPP1 to VNN1 Output VPP2 to VNN2 Output HVOUTP1 HVOUTN1 HVOUTP2 HVOUT N2 VPP3 to VNN3 Output HVOUT P3 HVOUTN3 ON ON ON OFF OFF OFF ON OFF OFF OFF OFF ON OFF OFF OFF ON OFF OFF OFF OFF ON OFF OFF OFF OFF ON OFF OFF OFF ON OFF OFF OFF ON ON ON OFF
OFF
OFF
OFF OFF OFF ON OFF
OFF
OFF
OFF OFF OFF ON OFF
OFF
OFF
OFF
OFF
OFF
OFF OFF
OFF OFF
OFF OFF
4
MD1711
Truth Table for Channels A and B (For SEL = H)
Logic Control Inputs SEL EN Clamp 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 X HVEN1/ POS2 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 X HVEN2/ NEG2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 X POS/ POS1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 X NEG/ NEG1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 X VPP1 to VNN1 Output HVOUTP1 HVOUTN1 OFF OFF ON ON OFF OFF ON ON OFF OFF ON ON OFF OFF ON ON OFF OFF ON ON OFF OFF ON ON OFF OFF ON ON OFF OFF ON ON OFF OFF ON OFF ON OFF ON OFF ON OFF ON OFF ON OFF ON OFF ON OFF ON OFF ON OFF ON OFF ON OFF ON OFF ON OFF ON OFF ON OFF VPP2 to VNN2 Output HVOUTP2 HVOUTN2 VPP3 to VNN3 Output HVOUTP3 HVOUTN3
OFF
OFF
OFF
OFF
ON
OFF
ON
OFF
OFF
ON
ON
OFF
OFF
OFF
ON
OFF
ON
ON
ON
OFF
ON
ON OFF
ON OFF
ON OFF
Test Circuit for Channel A
1/2 of MD1711
DVDD2
3x TC6320
VPP1 Out-PA 1 10nF GP A1 HV OUTPA1
DV DD2
+100 V
+10V
AV DD1 Out-NA1 10nF GNA 1
HVout A
+10V DV DD1 +10V DV DD2 +3.3V VLL EN PO SA / POS1A NEGA / NEG1A HVEN1A / POS2A HVEN2 A / NEG2A Clam pA SEL Channel A Control Logic and Level Translation
HV OUTNA1 VNN1 -100V
RLOAD 100
VPP2
DVDD1
+50 V
Out-PA 2
10nF
GP A2 HV OUTPA2
DVDD1
Out-NA2
10nF
GNA 2
HV OUTNA2 VNN2 -50V
AG nd DG nd Out-PA 3 -10V AV SS DV SS
DV SS DVDD1
GP A3 HV OUTPA3 GNA 3
Out-NA3
HV OUTNA3
Note: Only one of the two circuit channels is shown.
5
MD1711
Timing Diagram (EN = H, SEL = ClampA = L)
VLL HVEN1A / POS2A 0V VLL HVEN2A / NEG2A 0V VLL POSA / POS1A 0V VLL NEGA / NEG1A 0V fout VPP1 VPP2
HVOUT A
0V VNN2
VNN1 tr, rise time from 0.9VNN1 to 0.9VPP1 tf, fall time from 0.9VPP1 to 0.9VNN1
tr, rise time from 0.9VNN2 to 0.9VPP2
tf, fall time from 0.9VPP2 to 0.9VNN2
3.3V IN 0V tPH 10V OUT 0V
10 % 90% 50% 50%
tPL
90% 10%
tr
tf
6
MD1711
Block Diagram / Typical Application Circuit
+100V
DV DD2
1F
10nF
DV 1 DD DV 2 DD AV 1 DD
DV DD2
10nF
-100V 1F
+100V
DV DD 1
1F
Piezoelectric Transducer A
10nF
DV DD 1
POSA / POS1A
10nF
NEGA / NEG1A HVEN1A / POS2A HVEN2A / NEG2A ClampA
-100V 1F
V SS DV DD1
V
LL
SEL EN
Control Logic and Level Translate
DV DD2
+100V 1F
10nF
DV DD2
POSB / POS1B NEGB / NEG1B HVEN1B / POS2B HVEN2B / NEG2B
DV DD1
10nF
-100V 1F
+100V 1F
ClampB
10nF
DV DD1
Piezoelectric Transducer B
10nF
-100V 1F
AV SS DV SS AGND DGND
V SS DV DD1
Supertex MD1711
Supertex TC6320
7
MD1711
MD1711: Pin Description
VLL AVDD1 DVDD1 Logic supply voltage. Supplies analog circuitry portion of the gate driver. Should be at the same potential as DVDD1. Gate drive supply voltage. Supplies digital circuitry portion of the gate driver and the main output stage for Out-PA2, Out-NA2, OutNA3, Out-PB2, Out-NB2, and Out-NB3. Should be at the same potential as AVDD1. Gate drive supply voltage. Supplies digital circuitry portion of the gate driver and the main output stage for Out-PA1, Out-NA1, OutPB1, and Out-NB1. Can be at a different potential than DVDD1. Gate drive supply voltage for Out-PA3 and Out-PB3. Supplies digital circuitry portion and the main output stage. Should be at the same potential as AVSS. Negative driver supply for Out-PA3, Out-PB3 and bias circuits. They are also connected to the IC substrate. They are required to connect to the most negative potential of voltage supplies. Digital Ground. Analog Ground. Logic input control for channel A. When SEL = L, the pin is POSA. When SEL = H, the pin is POS1A. Logic input control for channel A. When SEL = L, the pin is NEGA. When SEL = H, the pin is NEG1A. Logic input control for channel A. When SE L= L, the pin is HVEN1A. When SEL = H, the pin is POS2A. Logic input control for channel A. When SEL = L, the pin is HVEN2A. When SEL = H, the pin is NEG2A. Used with SEL = H. Logic input control for Out-PA3 and Out-NA3. Connect to ground when SEL = L. Output P-Channel gate drivers for channel A Output N-Channel gate drivers for channel A Logic input control for channel B. When SEL = L, the pin is POSB. When SEL = H, the pin is POS1B. Logic input control for channel B. When SEL = L, the pin is NEGB. When SEL = H, the pin is NEG1B. Logic input control for channel B. When SEL = L, the pin is HVEN1B. When SEL = H, the pin is POS2B. Logic input control for channel B. When SEL = L, the pin is HVEN2B. When SEL = H, the pin is NEG2B. Used with SEL = H. Logic input control for Out-PB3 and Out-NB3. Connect to ground when SEL = L. Logic input select. See truth tables for SEL = L and SEL = H. Logic input enable control. When EN = L, all P-channel output drivers are high and all N-channel output drivers are low. Output P-Channel gate driver for channel B Output N-Channel gate driver for channel B
DVDD2 DVSS AVSS DGND AGND POSA / POS1A NEGA / NEG1A HVEN1A / POS2A HVEN2A / NEG2A CLAMPA Out-PA1, Out-PA2, Out-PA3 Out-NA1, Out-NA2, Out-NA3 POSB / POS1B NEGB / NEG1B HVEN1B / POS2B HVEN2B / NEG2B CLAMPB SEL EN Out-PB1, Out-PB2, Out-PB3 Out-NB1, Out-NB2, Out-NB3
8
MD1711
Pin Configuration 48-Lead LQFP/TQFP (1.4mm)
Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 Function POSA/POS1A NEGA/NEG1A HVEN1A/POS2A HVEN2A/NEG2A CLAMPA AVDD1 AGND CLAMPB HVEN2B/NEG2B HVEN1B/POS2B NEGB/NEG1B POSB/POS1B SEL AVSS AVSS DVSS Out-PB3 DGND DVDD1 Out-PB2 DVDD2 Out-PB1 N/C Out-NB1 Pin 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 Function DVDD2 DGND Out-NB2 DVDD1 Out-NB3 DGND DVDD1 Out-NA3 DVDD1 Out-NA2 DGND DVDD2 Out-NA1 N/C Out-PA1 DVDD2 Out-PA2 DVDD1 DGND Out-PA3 DVSS VLL EN AVSS
Doc. # DSFP-MD1711 A062806
9
Package Outline 48-Lead LQFP/TQFP Package Outline (FG)
7x7x1.4mm body, 0.50mm pitch
D D1
E
E1 Note 1 (Index Area D1/4 x E1/4) L2 48 1 b e L L1 Seating Plane Gauge Plane
Top View
View B A A2 Seating Plane A1
View B
Side View
Note 1: A Pin 1 identifier must be located in the index area indicated. The Pin 1 identifier may be either a mold, or an embedded metal or marked feature.
Symbol MIN Dimension (mm) NOM MAX
Drawings not to scale.
A 1.40 1.60
A1 0.05 0.15
A2 1.35 1.40 1.45
b 0.17 0.22 0.27
D 8.80 9.00 9.20
D1 6.80 7.00 7.20
E 8.80 9.00 9.20
E1 6.80 7.00 7.20
e 0.50 BSC
L 0.45 0.60 0.75
L1 1.00 REF
L2 0.25 BSC
0O 3.5O 7O
JEDEC Registration MS-026, Variation BBC, Issue D, Jan. 2001.
Doc. #: DSPD-48LQFPFG B032607

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